The extremely high switching speeds attainable with GaAs integrated circuits (IC's) make them very attractive for key portions of high speed systems. However, it is necessary that the GaAs ICs interface with the high speed silicon ICs used in the remainder of such high-speed systems. This has proven very difficult to achieve in practice because the dominant silicon IC technology for high speed applications is Emitter Coupled Logic (ECL) (typically F 100K or 10KH series made by Fairchild and Motorola, respectively) with logic swings (.DELTA.V.sub.L) that are quite low, typically 600 mV to 800 mV. Such low logic swings make it essential to position the logic input threshold voltage, V.sub.th, of a GaAs IC interfacing to ECL circuits precisely at the ECL threshold, or center of the ECL logic swing, which is called V.sub.BB in ECL terminology. Practically, if V.sub.th is not within of the order of 100 mV of V.sub.BB, the noise margin for logic input signals with the same polarity as the V.sub.th -V.sub.BB input threshold voltage error will be substantially degraded, along with dynamic response characteristics. Input threshold compatibility is very difficult to achieve in Field Effect Transistor (FET) logic because FETs do not have the extremely tight threshold voltage control of approximately 10 mV .DELTA.V.sub.BE that bipolar transistors inherently have. Further, the temperature coefficients of V.sub.th for GaAs MESFET logic circuits are not a good match for ECL thresholds. Even F 100K and 10KH versions of ECL do not match each other in this regard, let alone normal (uncompensated) GaAs circuits. The threshold control problem increases in such GaAs MESFET logic circuits such as Capacitor Diode FET Logic (CDFL) which use the standard ECL power supply range (V.sub.DD (GaAs)=V.sub.CC (ECL) =0.0 V and V.sub.EE (GaAs)=V.sub.EE (ECL) =-5.2 V). In such circuits, the sources of the switching D-MESFETS are connected to a separate intermediate V.sub.SS potential, typically V.sub.SS .congruent.-3.4 V (.+-.0.15 V), and hence it is to this V.sub.SS potential that the input threshold is referenced, as opposed to V.sub.CC in ECL. Hence any tolerance change in the V.sub.SS supply potential, (V.sub.DD -V.sub.SS), results in an identical change in the logic threshold voltage (V.sub.DD -V.sub.th) relative to ECL where V.sub.CC (V.sub.CC in an ECL circuit is the equivalent of V.sub.DD in a GaAs circuit) is the reference. In summary, achieving ECL input level compatibility in other than differential-input GaAs logic circuits over reasonable temperature range of 0 to +85.degree. C. or -55.degree. C. to +125.degree. C., or power supply tolerance of .+-.5% on V.sub.SS has not proven possible. This represents a critical problem in achieving widespread use of the GaAs IC technology in high speed electronic systems.